To design R-S Flip Flop

Aim

To design R-S Flip Flop

Apparatus Required:

Digital trainer kit, IC 7400, IC 7402, IC 7408, Connecting wires

Theory

The logic circuits that incorporate memory cells are called sequential logic circuits; their output depends not only upon the present value of the input but also upon the previous values. Sequential logic circuits often require a timing generator (a clock) for their operation. Flip flops are actually an application of logic gates. With the help of Boolean logic you can create memory with them. Flip flops can also be considered as the most basic idea of a Random Access Memory [RAM]. When a certain input value is given to them, they will be remembered and executed, if the logic gates are designed correctly. Usually there are two outputs, Q and its complementaryvalue.

R-S Flip-Flop

The fundamental latch is the simple SR latch, where S and R stand for set and reset respectively. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is present on the output marked Q. Normally, in storage mode, the S and R inputs are both low, & feedback maintains the outputs in a constant state, with Q and the complement of Q. If S (Set) is given with high while R is held low, then the Q output is forced high; similarly, if R (Reset) is given with high while S is held low, then the Q output is forced low. For S & R both high, output is invalid. It is an invalid state because the values of both Q and Q’ are 0. They are supposed to be compliments of each other. Normally, this state must be avoided.

A clock pulse [CLK] is given to the inputs of the AND Gate. When the value of the clock pulse is ‘0’, the outputs of both the AND Gates remain ‘0’. As soon as a pulse is given the value of CLK turns ‘1’. This makes the values at S and R to pass through the NOR Gate flip flop.