Verify the truth table of a D flip-flop (7474)

Aim

Verify the truth table of a D flip-flop (7474)

Apparatus Required:

Logic trainer kit, Flip-flop ICs- 7474, wires.

Theory

D flip flop also called as delay flip flop where it can be used to introduce a delay in the digital circuit by changing the propagation delay of the flip flop. Here the input data bit at D will reflects at the output after a certain propagation delay.

Characteristic Equation:Q’ = D Q’ + D Q Q’ = D

D Flip Flop with Preset and ClearPreset is the input to the D flip flop which sets the output data to High i.e. 1. and Clear is also an input which clears the output data or output state. A high Preset forces Q to 1; a high Clear resets Q to 0. Figure shows clocked flip flop with Preset and Clear inputs.

Clocked D Flip-Flop with Preset and ClearIn the above circuit irrespective of the AND gates out, if the PRESET input is high the OR gate out directly sets the S input which makes Q to 1and in the same way if CLEAR input is high it resets the Q to 1.

Procedure:

1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

Result:

Thus the D Flip flop was designed and their truth table is verified.

Precautions

1. All connections should be made neat and tight.
2. Digital lab kits and ICs should be handled with utmost care.
3. While making connections main voltage should be kept switched off.
4. Never touch live and naked wires.