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Home Electrical and Electronics Digital Electronics Design and verification of the truth tables of Half and Full adder circuits.
Digital Electronics Lab Experiments

Design and verification of the truth tables of Half and Full adder circuits.



Aim

Design and verification of the truth tables of Half and Full adder circuits.

Apparatus Required:

Logic trainer kit, NAND gates (IC 7400), XOR gates (IC 7486), AND gates (IC 7408), wires.

Theory:

Half adder:

Truth Table for Half Adder

Input Output
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

K-Map for SUM
HalfAdder using NAND Gates Only

Full Adder:A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken from OR Gate.

Truth Table for Full Adder

Input Output
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 1
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

K-Map for Sum Carry
Full Adder using basic Gates
Full Adder using NAND Gates only

Procedure:

  1. Connections are given as per circuit diagram.
  2. Logical inputs are given as per circuit diagram.
  3. Observe the output and verify the truth table.
  4. Result:

    Thus the half adder &full adder was designed and their truth table is verified.

    Precautions

  5. All connections should be made neat and tight.
  6. Digital lab kits and ICs should be handled with utmost care.
  7. While making connections main voltage should be kept switched off.
  8. Never touch live and naked wires.