New York, NY IMG HI 58° LO 56° Home About Contact
IMG-LOGO
Home Electrical and Electronics Digital Electronics Design of Modulo-4 Counter Using J K Flip flop.
Digital Electronics Lab Experiments

Design of Modulo-4 Counter Using J K Flip flop.



Aim

Logic trainer kit, J-K Flip-flop IC - 7476 wires.

Apparatus Required:

Logic trainer kit, D Flip-flop IC - 7474 wires.

Theory

The Johnson counter is a modification of ring counter. In this the inverted output of the last stage flip flop is connected to the input of first flip flop. If we use n flip flops to design the Johnson counter, it is known as 2n bit Johnson counter or Mod 2n Johnson counter. This is an advantage of the Johnson counter that it requires only half number of flip flops that of a ring counter uses, to design the same Mod. The main difference between the 4 bit ring counter and the Johnson counter is that is in ring counter, we connect the output of last flip flop directly to the input of first flip flop. But in Johnson counter, we connect the inverted output of last stage to the first stage input. The Johnson counter is also known as Twisted Ring Counter, with a feedback. In Johnson counter the input of the first flip flop is connected from the inverted output of the last flip flop. The Johnson counter or switch trail ring counter is designed in such a way that it overcomes the limitations of ring counter. Mainly it reduces the number of flip flops required for designing the circuit.

Operation

  • Initially, a short negative going pulse is applied to the clear input of all flip-flops. This will reset all the flip-flops. Hence, initially the o/ps are Q3 Q2 Q1 Q0 = 0000.
  • But Q′ 3 = 1 and since it is copied to ? 0 it is also equal to 1.
  • ? 0= 1 and ? = 1 initially.
  • On the first negative edge of clock arrives at first f/f. o/p of ? 0= 1.
  • after 1st –ve edge clock the o/ps of f/fs will be,Q3 Q2 Q1 Q0 = 0001
  • On second –ve clock o/p of 2nd f/f will be 1 i.e ? 1= 1.
  • Q3 Q2 Q1 Q0 = 0011
  • Similarly for 3rd –ve edge clock, Q3 Q2 Q1 Q0 = 0111
  • For 4th –ve edge clock, Q3 Q2 Q1 Q0 = 1111
  • Now as soon as 5th –ve edge is arrived o/p of 1st f/f becomes 0 i.e ? 0= 1 i.e Q3 Q2 Q1 Q0 = 1110 - This operation continues till the o/p is reached to zero o/p state. i.e Q3 Q2 Q1 Q0 = 0000
Logic Diagram
Waveforms for Johnson's Counter

Truth Table for a 4-bit Johson Ring Counter

CLock Pulse No FFA FFB FFC FFD
1 1/ 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1

Procedure:

  1. Connections are given as per circuit diagram.
  2. Logical inputs are given as per circuit diagram.
  3. Observe the output and verify the truth table.
  4. Result:

    Thus the Johnson counter was designed and their truth table is verified.

    Precautions

  5. All connections should be made neat and tight.
  6. Digital lab kits and ICs should be handled with utmost care.
  7. While making connections main voltage should be kept switched off.
  8. Never touch live and naked wires.