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Digital Circuit System Lab Experiments

To design J-K Flip-Flop



Aim

To design J-KFlip-Flop

Apparatus Required:

Digital trainer kit, IC 7411, IC 7402, Connecting wires.

Theory

The logic circuits that incorporate memory cells are called sequential logic circuits; their output depends not only upon the present value of the input but also upon the previous values. Sequential logic circuits often require a timing generator (a clock) for their operation. Flip flops are actually an application of logic gates. With the help of Boolean logic you can create memory with them. Flip flops can also be considered as the most basic idea of a Random Access Memory [RAM]. When a certain input value is given to them, they will be remembered and executed, if the logic gates are designed correctly. Usually there are two outputs, Q and its complementaryvalue.

J-K Flip-Flop

A J-K flip flop can also be defined as a modification of the S-R flip flop. The only difference is that the intermediate state is more refined and precise than that of a S-R flip flop. The behavior of inputs J and K is same as the S and R inputs of the S-R flip flop. When both the inputs J and K have a HIGH state, the flip-flop switches to the complement state. So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches toQ=1. The output may be repeated in transitions once they have been complimented for J=K=1 because of the feedback connection in the JK flip-flop. This can be avoided by setting a time duration lesser than the propagation delay through the flip-flop. The restriction on the pulse width can be eliminated with a master-slave or edge-triggered construction.

jk-flop-flop-block-diagram&logic-circuit

The combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip- flop, i.e., change its output to the logical complement of its current value.

Procedure:-

  1. Place the breadboard gently on the observationtable.
  2. Fix the IC which is under observation between the half shadow lineof breadboard, so there is no shortage ofvoltage.
  3. Connect the wire to the main voltage source (Vcc) whose other end is connected to last pin of the IC (14 place from thenotch).
  4. Connect the ground of IC (7th place from the notch) to the ground terminal provided on the digital labkit.
  5. Give the input at the gate of the ICs by using connectingwires
  6. Connect output pins to the led on digital lab kit.
  7. Switch on the powersupply.
  8. If led glows then output is true, if it doesn’t glow output is false, which is numerically denoted as 1 and 0respectively.
  9. The values of the outputs aretabulated.

Precautions:

  1. All ICs should be checked before starting theexperiment.
  2. All the connection should betight.
  3. Always connect ground first and then connectVcc.
  4. Suitable type wire should be used for different types ofcircuit.
  5. The kit should be off before changing theconnections.
  6. After the completion of experiment, switch off the supply of theapparatus.

Result:J-K flip-flop is designed and its truth table is verified.

Questions:

Q1:How is a J-K flip-flop made totoggle?

Ans:When j=k=1 then the race condition is occurs that means both output wants to be high. Hence, there toggle condition is occurs.

Q2:A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is?

Ans:The flip flop is sensitive only to the positive or negative edge of the clock pulse. So, the flip-flop toggles whenever the clock is falling/rising at edge. Thus, the output curve has a time period twice that of the clock. Frequency is inversely related to time period and hence frequency gets halved, so a 10 kHz square wave

Q3:What is the significance of the J and K terminals on the J-Kflip-flop?

Ans:The letters J & K were chosen in honour of Jack Kilby, the inventory of the integrated circuit.