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Home Electrical and Electronics Digital Circuit System To examine parity generator/checker circuit.
Digital Circuit System Lab Experiments

To examine parity generator/checker circuit.



Aim

To examine parity generator/checker circuit.

Apparatus Required:

Digital trainer kit, IC 7486, IC 7400, Connecting wires.

Theory

A parity bit is used for the purpose of detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the number of 1’s either odd or even. The message including the parity bit istransmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker. In odd parity the added parity bit will make the total number of 1’s an oddamount. In a three bit odd parity generator the three bits in the message together with the parity bit are transmitted to their destination, where they are applied to the parity checker circuit. The parity checker circuit checks for possible errors in the transmission Since the information was transmitted with odd parity the four bits received must have an odd number of 1’s. An error occurs during the transmission if the four bits received have an even number of 1’s, indicating that one bit has changed during transmission. The output of the parity checker is denoted by PEC (parity error check) and it will be equal to 1 if an error occurs, i.e., if the four bits received has an even number of 1’s

Odd Parity Generator

Input (Three Bit message) Output (Old Parity bit)
A B C P
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

From the truth table the expression for the output parity bit is,

P (A, B, C) = Σ m (0, 3, 5, 6) Also written as,

P = ABC + ABC + ABC + ABC

P = ABC + ABC + ABC + ABC

P = (A⊕B⊕C)

Circuit Diagram Odd Parity Geerator

odd-parity-generator

Odd Parity Checker

Input (Four Bit message Recieved) Output (Parity Error Check)
A B C P X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

From the truth table the expression for the output parity checker bit is,

X (A, B, C, P) = Σ (0, 3, 5, 6, 9, 10, 12, 15)

The above expression is reduced as,

X = (A⊕B⊕C⊕P)

Circuit Diagram Odd Parity Geerator

odd-parity-checker

Procedure:-

  1. Connections are given as per the circuitdiagrams.
  2. For all the ICs 7th pin is grounded and 14th pin is given +5 Vsupply.
  3. Apply the inputs and verify the truth table for the Parity generator andchecker.

Precautions:

  1. All ICs should be checked before starting theexperiment.
  2. All the connection should betight.
  3. Always connect ground first and then connectVcc.
  4. Suitable type wire should be used for different types ofcircuit.
  5. The kit should be off before changing theconnections.
  6. After the completion of experiment, switch off the supply of theapparatus.

Result:The design of the three bit odd Parity generator and checker circuits was done and their truth tables were verified.

Questions:

Q1:Which error detection method uses one’s complementarithmetic?

Ans:A checksum can be generated simply by adding bits. Hence, one’s complement arithmeticuses checksum.

Q2:Which error detection method consists of just one redundant bit per data unit?

Ans:Simple parity check method consists of just one redundant bit per dataunit.

Q3:How many types of parity bits arefound?

Ans:There are two types of parity bits, namely even parity and odd parity.

Q4:What is a paritybit?

Ans:A simple form of error detection is achieved by adding an extra bit to the transmitted word.The additional bit is known as parity bits.